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FS3861 Data Sheet
Intelligent Charger Management Controller
Rev. 1.0 Dec. 2004
Fortune Semiconductor Corp.
TD-0412012
CR-004
FS3861
Taipei Office:
28F, No.27, Sec. 2, Zhongzheng E. Rd., Danshui Town, Taipei County 251, Taiwan Tel.G 886-2-28094742 FaxG 886-2-28094874 Web Site: http://www.fsc.com.tw
Hsinchu Office:
4F-5, No. 30, Taiyuan St., Zhubei City, Hsinchu County 302, Taiwan Tel.G 886-3-5525296 FaxG 886-3-5525946
Shenzhen Technical Support:
14F, Dingxin Building West, No. 1, Liuxian Blvd., Xili Town, Nanshan District Shenzhen, Guangdong 518055, P. R. China Tel. :86-755-26528742 Fax :86-755-26528940
This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed by Fortune Semiconductor Corporation as a result of the use of this product. No rights under any patent accompany the sale of the product.
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Table of Contents
Page No.
1. 2. 3. 4. 5. 6. 7. 8. 9.
GENERAL DESCRIPTION ............................................................................................................. 4 FEATURES......................................................................................................................................... 4 APPLICATIONS................................................................................................................................ 4 ORDERING INFORMATION ......................................................................................................... 5 PIN CONFIGURATION ................................................................................................................... 6 PIN DESCRIPTION .......................................................................................................................... 7 FUNCTIONAL BLOCK DIAGRAM............................................................................................... 8 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 9 ELECTRICAL CHARACTERISTICS............................................................................................ 9 DC Characteristics ............................................................................................................................. 9 10. FUNCTIONAL DESCRIPTION .................................................................................................... 10 10.1 Typical Charging Scheme...................................................................................................... 10 10.1.2 Charging Application Circuit........................................................................................... 12 10.1.3 Operation Flow Chart of Charging Application............................................................... 13 10.2 The Architecture of FS3861................................................................................................... 14 10.3 The organization of FS3861 MCU and its program & data memory space ..................... 14 10.3.1 Program Memory Organization ...................................................................................... 14 10.3.2 Data Memory Organization............................................................................................. 15
10.3.2.1 System Special Register ..........................................................................15 10.3.2.2 Peripheral Special Register.........................................................................17 10.3.2.3 PWM (PDM) Voltage Generation................................................................18 10.3.2.4 Timer Interrupt Register, LED output displays and General I/O data bits...................22
11. INSTRUCTION SET...........................................................................................23 12. PACKAGE INFORMATION.................................................................................34
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1. General Description
The FS3861 is a low-cost high-performance Li+ single-cell 4.2v/4.1v battery charger control IC which includes all the required constant-current and constant-voltage regulations of charge functions addressed for linear charger mode operations in typical four phases: pre-charging conditioning, constant current, constant voltage, and charge terminations (usually based on the minimum current reached). The maintenance re-charge (or called post-charge stage) proceeds if the full-charged battery voltage is once again lower than the desired full-capacity voltage because of consumptions of its capacity which occurs either at the battery's internal voltage drop across its terminals, or at the use of the battery. This chip with built-in 8-bit RISC-type MCU with 1K-word OTP PROM and 64-Byte data RAM employs a minimum numbers of external transistor and passive resistor & capacitor devices to fulfill complete charger implementations at cost-effective solutions. The available 16-pin SSOP-16 package is offered for balanced area and cost effective requirements for size-sensitive applications. The FS3861 is suitable for the control of charge sequences of a variety of portable battery-powered applications, such as cellular phone's travel and base charger devices, digital camera, digital-video camcorder (DV), MP3 player ,etc. Features of the PWM voltage generation is complimentary to the provision of look-up voltage table for use at specific intermediate charge voltages or detected values for the comparator's function. 2 LED output for charge status. Optional Temp and battery ID input through voltage sense input. Low-cost peripheral components of capacitor and resistor combinations for minimum BOM cost in manufacturing considerations. Development kit of LQFP-64 ICE evaluation (EV) board and reference charge program available for prototype design and facilitating debug use. SSOP-16 Package.
3. Applications
Cellular phone external base or built-in charger MP3 player External charger through USB Digital still camera (DSC) Digital video camcorder (DV) Portable electronic device charger, etc.
2. Features
Ideal for the Li-ion/polymer Single-Cell 4.2v/4.1v charge control. Built-in 8-bit RISC-typed MCU with 1K-word OTP program ROM and 64-Byte data RAM. Integrated voltage and current regulation with programmable charge current. Supports typical Li+ battery's charge sequences such as pre-charge (trickle-mode charge), C-C (constant-current charge), C-V (constant-voltage charge), charge terminations, and re-charge operations. Batter than 1% charge voltage regulation accuracy. Charge operation can be monitored by the external host through the general I/O data bus.
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4. Ordering Information
Product Number Description Package Type FS3861-ICE Customer can program the compiled hex code into LQFP-64 EPROM through the FSC's development kit for evaluation and facilitating debug. FS3861A-nnnV Customer's compiled hex code can be programmed SSOP-16 by FSC or customer itself into EPROM at factory before shipping. Note1: Code number (nnnV) is assigned for customer. Note2: Code number (nnn = 001~999); Version (V = A~Z).
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5. Pin Configuration
FS3861 SSOP16 Package
FS3861 ICE LQFP64 Package
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6. Pin Description
Name SNS VCC RST_/VPP TEST GPIO[0] GPIO[1] GND GPIO[2] OSC PWMC LED0 LED1 TS VBATID VBAT CC I/O I I I I I/O I/O I/O I I O O I I I O Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Current sensing using an external sensing resistor RSNS Supply voltage Active low reset or as active high OTP program write Test mode input. Test=1 is the normal mode. Test Mode is initiated while Test=0 before reset. This pin is suggested pulled inactive high for regular operation without Test Mode. General purpose bi-directional I/O pin 0 General purpose bi-directional I/O pin 1 Ground General purpose bi-directional I/O pin 2 Oscillator input. Connect to an external resistor R=200k, the oscillator frequency is around 4.5MHz PWM capacitor input for selection of the RC time constant in generating voltage reference. Source or sink LED0 display Source or sink LED1 display Battery temperature sensing input Battery ID-type selected by the voltage drop across the series resistor. Battery ID is for identification of either thick, thin battery or other selected types Battery input voltage Charge control output to drive pass transistor
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7. Functional Block Diagram
VCC Current Reference 25mA 50mA 75mA 100mA 125mA 150mA 250mA 350mA 400mA 450mA 500mA 650mA 750mA 850mA 950mA 1050mA Voltage Reference 1.2V 1.4V 2.4V 2.8V 3.2V 3.4V 3.6V 4.0V 4.1V 4.2V 4.23V 4.25V 4.3V VPWM Embedded Microcontroller CMPNSEL[2:0] ENCVref
8 to 1 MUX
SNS
ENCCref CURSEL[3:0] ENCC CC
ENBGR_
Reference Voltage
RST_/ VPP
1 KByte OTP EPROM 3
16 to 1 MUX
VOLSEL[3:0] ENCV GPIO
GPIO [2:0] LED [1:0] 2 OVLO OVLO UVLO NORM
16 to 1 MUX
ENOVLO PWEN
PWCS [2:0] 4MHz
TS VBATID VBAT SNS IC TEMP
VBAT VBATID TS
Pulse Density Modulation
Internal Oscillator
VPWM 1.2V 1.4V 1.5V 2.0V 2.4V 2.5V 2.6V 2.8V 3.0V 3.1V 3.2V 3.3V 3.4V 3.6V 3.9V 4.0V 4.1V 4.15V 4.2V 4.23V 4.25V 4.3V CMPPSEL[4:0] 25mA 50mA 75mA 100mA 125mA 150mA
32 to 1 MUX
PWMC
OSC
GND
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8. Absolute Maximum Ratings
Parameter Supply Voltage to Ground Potential Applied Input Voltage for Programming OTP EPROM Applied input voltage of other pins Operating Temperature Storage Temperature Soldering Temperature/Time Item VCC VPP VIO TA TSTG TSOLDER Rating -0.3 to 5.5 -0.3 to 13 -0.3 to VCC+0.3 -20 to 70 -40 to 125 260C/10 Sec Unit V V V C C C/Sec
9. Electrical Characteristics
DC Characteristics
(TA=25C, unless otherwise noted) Symbol Parameter VCC Operation Power Voltage Input VCC current on charge ICC(VCC) mode (regular operation) Input VCC current on sleep ICC(Sleep) mode VIH VIL VOH VOL ISINK ISOURCE Digital I/O input high voltage Test Conditions VCC > VCC (min) VBATU VCC; VCC is OFF 2.5 -0.3 0.5 0.4 10 0.1 Min. 4.35 Typ. 5.0 1 Max. 5.5 3 25 5.5 1.0 1.0 0.8 50 1 Unit V mA A V V VCC VCC mA mA
VREF
VCREF FRC
VCC Voltage applied 4.35v to 5.5v VCC Voltage applied 4.35v Digital I/O input low voltage to 5.5v Digital I/O output high voltage Reference to VCC Digital I/O output low voltage Reference to VCC Output sink current of Digital I/O output sink current digital I/O pins set as output mode Output source current of Digital I/O output source digital I/O pins set as input current mode The voltage select register VOSEL[3:0] = 4'b1100 (the register CVCTL at the data Internal reference voltage memory address=0BH), measured from voltage supply VCC region 4.35V to 5.50V Build in reference voltage TA=0~60C temperature coefficient External R=200k[ Internal RC oscillator
3.9
4.3
V
150 4
ppm/C MHz
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10. Functional Description
10.1 Typical Charging Scheme
10.1.1 Typical Charging Conditions and Phases
The FS3861 uses flexible control schemes of charger's current and voltage regulations in conjunction with the built-in 8-bit RISC-type MCU core running at typical 4 MHz for desired charge sequence controls during its operations. It is embedded with the constant-current and constant-voltage regulations as well as the additional facilities of PWM voltages for user-defined intermediate voltage levels used for various applications. The external sensing resistors together with built-in parameters of the 8-bit MCU enable the device performing charge cycle operations through selections of small to larger charge current's amounts primarily for Li+ battery's linear mode charge applications, where the pulse-mode charging can be implemented using the internal hardware to control the charge sequences as implemented by the built-in MCU program code for various charger applications.
Fig.1 Typical Charge Profile
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The typical Li+ charge steps are mainly four stages to conduct: Pre-charge conditioning (or called trickle-mode charge, as the Phase-0 stage): where the low-voltage discharged battery typical lower than 3.0v (or 2.8v, depending on how the battery's parameters are set) gets wake-up by applying typical 1/10 of full-rate charge current (a small amount of selectable charge current, also called trickle current, such as 85mA of 850mA charge current ) until reaching the threshold voltage 3.0v. If the trickle current has been applied to the battery for more than 30 minutes by timer's measurement and not reaching the required 3.0v, it could be detected as bad battery without continuing to the next step of charge operations. Constant current charge (as Phase-1, referred as C-C stage): where the programmable constant current ranging from typical 250mA to 1,050mA is applied to the battery, until the battery voltage reaches to the full-level at 4.2v or similar value such as 4.1v or even 4.0v. Some applications require the constant current charge at USB current of 500mA when its power line at 5v is applied, and such charge stage can be implemented with selection of the current regulation at 500mA by setting the corresponding C-C reference bit and current select values at the specified control registers, as explained in details descriptions in later section. Constant voltage charge (shown as Phase-2, referred as C-V stage): using the regulated voltage at 4.2v reached at the constant current charge stage until the termination condition is met at the final low termination top-off current at smaller amount (such as 100mA which can be programmable to select), and then charges to the full capacity when termination occurs. Selections of the C-V charge's voltage level can be made with corresponding C-V enable and voltage select values at the individual specified control registers. Maintenance re-charge (shown as Phase-3 stage): can be called Post-charge stage, which is to resume charges to the battery when the battery's voltage drops is more than 0.1v (i.e. The battery terminal voltage becomes 4.10v or less from its full voltage at 4.20v) as a result of the internal resistor during its idle state through some time. If the battery has been taken off for use on its portable device, there is no re-charge check to conduct since the state transitions to the initial state without the battery itself. In some other cases, the preliminary charge stage which can be conducted as one step prior to the phase-0 to assure the battery to be through the charge sequences has working functions to perform. This stage would involve in applying constant-voltage charge pulses at defined level of 4.0v or so to the battery, which was examined to determine if it's at low voltage of 2.5v or less. The charge pulses applied to the battery for a short period of 15 intervals with 10 seconds high (at 4.0v voltage beats) and 5 seconds low (ground) each to examine if the battery voltage still remain low at 2.5v or less, which is then considered as defective and should be discarded. Sometimes another additional check-up procedure follows the termination of the C-V stage to assure the battery in proper waiting stage for operation. That is to have the battery stay idle from its charge termination at full voltage of 4.20v (or 4.1v, depending on the battery's manufacturer's parameters). Then the battery stays in for additional 10 (or 15, also an adjustable parameter) minutes, and then its voltage is examined to assure the terminal voltage won't be decreased to lower than 4.05v (or 3.95v if the situation prevails), then the battery is also determined as a defective one without reliable performance since it could be losing more than 0.15v within a short period of just 10 (or 15) minutes. These check-up procedures are optional. In brief summary, the typical Li+ battery charger's procedures could be summarized in the following few steps: pre-charge conditioning, constant-current (C-C), constant voltage (C-V) stage, charge termination and monitor to re-charge, etc. There might have some individual charge's current- or voltage-control schemes within the designated step to perform.
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10.1.2 Charging Application Circuit
Fig.2 FS3861 Application Circuit
The Fig.2 shows the typical FS3861 application circuit used at base or travel charger devices of a variety of cellular phone and other portable devices. The above application circuitry shows the chip connected with an one-cell Li+ 4.2v battery, which features battery ID (at the VBATID input pin) and temperature sense output (at TS pin) for relevant controls. Interface to external host is optional at the general I/O bus pins with connections to the host side which commands the base charger with monitor facilities to control the charger operations. The use of PNP or PMOS as the pass transistor realizes the control of C-C and/or C-V mode current/voltage regulations.
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10.1.3 Operation Flow Chart of Charging Application
Fig.3 is a typical example of operation state diagram.
Fig.10-3 Typical operation flow chart
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10.2 The Architecture of FS3861
The detailed architecture diagram of the FS3861 has already shown on Fig.7-1 for illustrations of its operations by the functional blocks, where the major facilities are constant-voltage (C-V) and constant-current (C-C) reference look-up table and regulation units as controlled by the MCU to realize the Li+ battery charge schemes. The FS3861 charger controller functions with illustrations of the current and voltage regulations, MCU, OTP ROM, and comparator implementing the linear-mode charge control. Note the built-in PWM (or called PDM, as named by the pulse density modulations) unit is complementary to the fixed voltage reference for proper generation of reference voltage to use in the intermediate charge control. Their VPWM levels subject to the PWM's setting of the fraction's bit and clock timing selects, as described in the later section of data memory register definitions, so the PWM's voltage level can then be used to perform specific voltage regulation in constant-voltage charge control to activate the output pin CC (charge control).
10.3 The organization of FS3861 MCU and its program & data memory space
The FS3861 charger controller employs FSC's proprietary RISC-architecture pipelined-mode high-performance 8-bit MCU core with built-in 1K Word program memory space and 64 Bytes of data memory space.
10.3.1 Program Memory Organization
CPU has a 10-bit program counter capable of address up to 1k x 16 program memory space. The reset vector is at 0000H and the interrupt vector is at 0004H.
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10.3.2 Data Memory Organization
The data memory is partitioned into three parts. The address 00H~07H areas are system special registers, like indirect address, indirect address pointer, status register, working register, interrupt flag and interrupt control register. The address 08H~1FH areas are peripheral special registers. The address 80H~BFH areas are general data memory. Content ( u means unknown or unchanged ) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset State
uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu C VDDIF VDDIE Z TMIF TMIE uuu0uuuu uuuuuuuu uuu00000 0uu00000
Address
Name
WDT Reset State
uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuu00000 0uu00000
00H IND0 01H IND1 02H FSR0 03H FSR1 04H STATUS 05H WORK 06H INTF 07H INTE 08H~1FH 80H~BFH
Use contents of FSR0 to address data memory Use contents of FSR1 to address data memory Indirect data memory, address pointer 0 GIE Indirect data memory, address pointer 1 PD DC WORK register NORMIF OVLOIF UVLOIF NORMIE OVLOIE UVLOIE Peripheral special registers General data Memory (64 bytes SRAM)
10.3.2.1. System Special Registers
IND0, IND1 : ADDRESS 00H, 01H The IND[1:0] registers at data memory address are not physical registers. Any instruction using the IND[1:0] registers actually access the data pointed by the FSR[1:0] registers. bit7~0 Use contents of FSR0 (IND0: Address 00H) or FSR1 (IND1: Address 01H) to address data memory
FSR0, FSR1 : ADDRESS 02H, 03H Indirect addressing pointers FSR0 and FSR1 correspond to IND0 and IND1 respectively. bit7~0 bit7~0 Indirect data memory, address pointer 0 (Address 02H) Indirect data memory, address pointer 1 (Address 03H)
STATUS : ADDRESS 04H The STATUS register contains the arithmetic status of the ALU. bit7 bit 7~5 bit 4 bit6 bit5 bit4 PD bit3 bit2 DC bit1 C bit0 Z
bit 3
unimplemented PD: Power Down Flag 1 = After power on reset or cleared by writing 0 (which shuts off oscillator clock, thus neither of the MCU clock or operation will be in conduct) 0 = By execution of the SLEEP instruction, but not the HALT instruction (which only turns off the MCU clock) unimplemented
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bit 2 DC: Digit Carry Flag (ADDWF, SUBWF instructions) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry Flag (~Borrow) Z: Zero Flag 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero : ADDRESS 05H Store temporary data
bit 1 bit 0
WORK bit7~0
INTF, INTE: ADDRESS 06H, 07H bit7 GIE bit7 bit6~5 bit4 bit3 bit2 bit1 bit0 bit6 bit5 bit4 bit3 bit2 bit1 NORMIF OVLOIF UVLOIF VDDIF NORMIE OVLOIE UVLOIE VDDIE bit0 TMIF TMIE
GIE: Global interrupt enable (Address 07H) unimplemented NORMIF, NORMIE: VDD within normal working range (4.35V~5.5V) Interrupt flag and enable. NORMIF can wake up MCU if MCU is in sleep mode. OVLOIF, OVLOIE: VDD over normal working range (VDD>5.5V) Interrupt flag and enable. UVLOIF, UVLOIE: VDD under normal working range (VDD<4.35V) Interrupt flag and enable. VDDIF, VDDIE: VDD > VBAT Interrupt flag and enable. Used when there is only VBAT and VDD is off. VDDIF can wake up MCU if MCU is in sleep mode. TMIF, TMIE: 16-bit Timer Interrupt flag and enable.
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10.3.2.2. Peripheral Special Registers
Content ( u means unknown or unchanged ) Address 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset State WDT Reset State
00uu0uuu uuuuuuuu 00uu0000 00uu0000 00000000 00000000 00000000 uuu0u000 00000000 uuuu0000 0000u000* 00000000* 0uuuu000
POWER ENBGR_ ENOVLO ENCMP RESULT OVLO UVLO NORM CMPOUT CCCTL ENCCref ENCC CURSEL[3] CVCTL ENCVref ENCV VOLSEL[3] CMPSEL CMPNSEL[2] CMPNSEL[1] CMPNSEL[0] CMPPSEL[4] CMPPSEL[3] PWDH PWM[15] PWM [14] PWM [13] PWM [12] PWM [11] PWDL PWM[7] PWM[6] PWM [5] PWM [4] PWM [3] PWDCON PWEN TMOUT TMOUT[7:0] TMCON TRST TMEN LEDCTL LED1EN LED1 LED0EN LED0 GPIO SPWMEN GPIO1OEN GPIO1 GPIO1PU SPWMO Unimplemented Unimplemented
00uu0uuu uuuuuuuu 00uu0000 00uu0000 CMPPSEL[2] CMPPSEL[1] CMPPSEL[0] 00000000 PWM [10] PWM [9] PWM [8] 00000000 PWM [2] PWM [1] PWM [0] 00000000 PWCS[2] PWCS[1] PWCS[0] uuu0u000 00000000 INS[2] INS[1] INS[0] uuuu0000 GPIO2OEN GPIO2 GPIO2PU 0000u000 GPIO0OEN GPIO0 GPIO0PU 00000000 uuuuuuuu 0uuuu000
VDDIN CURSEL[2] CURSEL[1] CURSEL[0] VOLSEL[2] VOLSEL[1] VOLSEL[0]
* Input Mode doesn't pull up. POWER : ADDRESS 08H bit7 ENBGR_ bit7 bit6 ENOVLO bit5 bit4 bit3 ENCMP bit2 bit1 bit0 -
bit6 bit5~4 bit3
bit2~0
ENBGR_: Enable the internal bandgap references of both the voltage and current regulations. This bit is active LOW enable. Thus, the procedure of enabling the current or voltage regulations is to enable the ENBGR_ before enabling the ENCCref, ENCC (ADDRESS 0AH) and ENCVref, ENCV (ADDRESS 0BH). ENOVLO: Enable the working voltage detection to assure the input voltage satisfied 4.35V < VCC < 5.5V. unimplemented ENCMP : The comparator enable bit enables the internal comparator for comparison between the measured input parameters (such as the battery voltage, sensed charged current, battery temperature, etc.) and the pre-set current or voltage values selected by the comparator select CMPPSEL[4:0] (ADDRESS 0CH). unimplemented
RESULT : ADDRESS 09H bit7 bit7 bit6 bit5 bit4 bit6 OVLO bit5 UVLO bit4 NORM bit3 CMPOUT bit2 bit1 bit0 VDDIN
unimplemented OVLO: Over voltage lock-out status READ ONLY register bit. UVLO: Under voltage lock-out status READ ONLY register bit. NORM: Normal status READ ONLY register bit.
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bit3 bit2~1 bit0 CMPOUT: The comparator output. unimplemented VDDIN: The status indicator (Read Only) of supply voltage VCC greater than VBAT, i.e. VDDIN is set high when VCC > VBAT. If there is no VCC and only the VBAT of battery is connected, then the VDDIN is set inactive low. : ADDRESS 0AH bit6 ENCC bit5 bit4 bit3 CURSEL[3] bit2 CURSEL[2] bit1 CURSEL[1] bit0 CURSEL[0]
CCCTL
bit7 ENCCref bit7 bit6 bit5~4 bit[3:0]
ENCCref: Enable constant current regulation reference current. ENCC: Enables the constant current regulation for constant current charge with desired current amount selected. unimplemented The 3-bits select CURSEL[3:0] selects constant current regulation reference current. The regulation current accuracy is 10% (unless otherwise noted). 0000 45mA 20mA 1000 410mA 0001 70mA 20mA 1001 460mA 0010 95mA 20mA 1010 500mA 0011 120mA 20mA 1011 650mA 0100 145mA 20mA 1100 750mA 0101 170mA 20mA 1101 850mA 0110 265mA 1110 950mA 0111 360mA 1111 1050mA
CURSEL[3:0] Select CURSEL[3:0] Select CVCTL
: ADDRESS 0BH bit6 ENCV bit5 bit4 bit3 VOLSEL[3] bit2 VOLSEL[2] bit1 VOLSEL[1] bit0 VOLSEL[0]
bit7 ENCVref bit7 bit6 bit5~4 bit[3:0]
ENCVref: Enable constant voltage regulation reference current. ENCV: Enables the constant voltage regulation for constant voltage charge with desired voltage amount selected. unimplemented The 3-bits VOLSEL[3:0] selects constant voltage regulation reference voltage. The regulation voltage accuracy is 3/4 1%. 0000 1.2V 1000 4.1V 0001 1.4V 1001 4.2V 0010 2.4V 1010 4.23V 0011 2.8V 1011 4.25V 0100 3.2V 1100 4.3V 0101 3.4V 1101 VPWM 0110 0111 3.6V 4.0V 1110 1111 Reserved Reserved
VOLSEL [3:0] Select VOLSEL [3:0] Select
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CMPSEL : ADDRESS 0CH bit7
CMPNSEL[2]
bit6
CMPNSEL[1]
bit5
CMPNSEL[0]
bit4
CMPPSEL[4]
bit3
CMPPSEL[3]
bit2
CMPPSEL[2]
bit1
CMPPSEL[1]
bit0
CMPPSEL[0]
Also refer to ENCMP (ADDRESS 08H) and CMPOUT (ADDRESS 09H) register bits. The bit CMPOUT is the compared output and would be set high on comparator's measured input value (like current across the sense resistor Rsns with selecting the desired measured item by setting the CMPNSEL[2:0]) match exactly with the positive input of the selected reference value. bit[7:5] CMPNSEL[2:0] select comparator negative input. 000 TS 001 VBATID 010 VBAT 011 SNS 100 101 110 111 ICTEMP Reserved Reserved Reserved
CMPNSEL [2:0] Select TS
VBATID VBAT SNS ICTEMP
The voltage of external thermistor, with either PTC (positive temperature) or NTC (negative temperature) coefficient, and is compared with VPWM for temperature measurements and subsequent control actions. The voltage of external Battery ID, and is compared with VPWM for determining the battery's types before charges. Battery voltage and will be compared with 2.5V, 2.6V, 3.0V, 3.9V,....4.25V, 4.3V, also shown on the voltage regulations. The current sensing voltage and will be compared with the 50mA, 100mA, 150mA to determine the termination current. The chips die body temperature measurement for prevention of excessive heat while in continuous operations.
bit[4:0]
CMPPSEL[4:0] select comparator positive input. 00000 VPWM 01000 2.8V 10000 4.0V 11000 85mA 20mA 00001 1.2V 01001 3.0V 10001 4.10V 11001 110mA 20mA 00010 1.4V 01010 3.1V 10010 4.15V 11010 130mA 20mA 00011 1.5V 01011 3.2V 10011 4.20V 11011 160mA 20mA 00100 2.0V 01100 3.3V 10100 4.23V 11100 185mA 20mA 00101 2.4V 01101 3.4V 10101 4.25V 11101 265mA 10% 00110 2.5V 01110 3.6V 10110 4.3V 11110 360mA 10% 00111 2.6V 01111 3.9V 10111 60mA 20mA 11111 410mA 10%
CMPPSEL [4:0] Select CMPPSEL [4:0] Select CMPPSEL [4:0] Select CMPPSEL [4:0] Select
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10.3.2.3. PWM (PDM) Voltage Generation
The VPWM which is one of the comparator's selected item by setting the CMPPSEL[4:0]==5'b00000 is the voltage level generated by the PWM function(pulse-width-modulation, or called pulse-density-modulation abbreviated as PDM, since the scheme here is using the PDM instead of the PWM for generating pulse clock signals), either selected by the hardware or software PWM module. The pulse density modulation clock enable bits used at hardware PWM mode can be selected on the contents of the registers PWDH[7:0] and PWDL[7:0] addressed at 0DH and 0EH, respectively. PWDH : ADDRESS 0DH bit6 PWM [14] bit5 PWM [13] bit4 PWM [12] bit3 PWM [11] bit2 PWM [10] bit1 PWM [9] bit0 PWM [8]
bit7 PWM[15] PWDL
: ADDRESS 0EH bit6 PWM [6] bit5 PWM [5] bit4 PWM [4] bit3 PWM [3] bit2 PWM [2] bit1 PWM [1] bit0 PWM [0]
bit7 PWM[7]
PWM[15:0]={PWDH[7:0],PWDL[7:0]} The PWM reference voltage is generated by using the derived divider chained-clocks for generation of the sub-digit voltage level. For example, the bit PWM [14] = PWDH [6] =1'b1 refers to the clock-chained derived clock to make the voltage-level divide-by-4, i.e., VCC / 2-2= VCC / 4. The following figure shows the PDM definition:
KKK
KKK
KKK
From above, we know that PDM[15] represents the same energy weighting of PWM[15] in the 16-bit period of time. PDM[15] can generate the same 32,768 counts of positive pulse, (PDM[15] = 1 = PWM[15]) or 0 count (PDM[15] = 0 = PWM[15]) as normal PWM[15] does in the 16-bit period of time. Also, PDM[14] can generate the same 16,384 counts of positive pulse, (PDM[14] = 1 = PWM[14]) or 0 count (PDM[14] = 0 = PWM[14]) as PWM[14] Fortune Semiconductor Corp.
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does, and so on. Then, we know that we may get the same energy weighting (or counts of positive pulse) in the 16-bit period of time if we set the same value on PDM[15:0] and PWM[15:0]. If we zoom into the 8-bit period of time from the beginning within the 16-bit period with the setting of PDM[15:0]= 1000-0000-0000-0000b = PWM[15:0], we will see that PDM offers better energy transformation than PWM does. PDM still offers half energy (128 counts of positive pulse) within the 8-bit period of time from the beginning within the 16-bit period, but PWM offers full energy (256 counts of positive pulse) within the same period. For example, if the PWM [15:0] =30A4H, then the voltage level is Full-Scale*(30A4H / FFFFH) = 0.19*Full-Scale and vice versa. Also note that the software PWM enable bit SPMWEN (ADDRESS 13H) should be set inactive low to enable the hardware PWM for the PWM generated specific voltage. PWDCON : ADDRESS 0FH bit7 bit[7:5] bit4 bit3 bit[2:0] PWCS [2:0] Select bit6 bit5 bit4 PWEN bit3 bit2 PWCS[2] bit1 bit0 PWCS[1] PWCS[0]
unimplemented PWEN: Enable Pulse Density Modulation clock output. unimplemented PWCS[2:0] selects Pulse Density Modulation clock input source. Setting as below: 000 001 010 011 100 4MHz/32 101 4MHz/64 110 4MHz/128 111 4MHz/256
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10.3.2.4. Timer Interrupt Register, LED output displays, and General I/O data bits
TMOUT : ADDRESS 10H bit7 bit6 bit5 bit4 bit3 TMOUT [7:0] bit2 bit1 bit0
TMOUT [7:0] is the output of the 8-bit counter, read-only register. TMCON : ADDRESS 11H bit7 TRST bit7 bit[6:4] bit3 bit6 bit5 bit4 bit3 TMEN bit2 INS[2] bit1 INS[1] bit0 INS[0]
bit2[2:0]
TRST: If set TRST=0, the MCU will reset the 8-bit counter. Then read TRST bit will get "1". unimplemented TMEN: Counter enable 1 = The 8-bit counter will be enabled 0 = The 8-bit counter will be disabled INS[2:0] selects timer interrupt source TMOUT[7:0] while Timer Clock source = 4MHz/32 = 128 kHz.
INS[2:0] selects the interrupt source TMOUT[7:0], as shown below, where the timer clock's master source is kept at 128KHz corresponding to INS[2:0]==3'b111. For example, if we want to use the timer clock at 64kHz, then INS[2:0]== 3'b110 should be set to get the corresponding timer clock; and if we want the timer activated at the divide-by-32 corresponding to TMOUT[7:0]==8'h20, the interrupt would be activated whenever the 64kHz clock has the count equal to 32 (or 20H). INS [2:0]
Interrupt Source
000
TMOUT[0] TMOUT[0]
Timer Clock Source
001
010
011
100
101
110
111
TMOUT[1] TMOUT[2] TMOUT[3] TMOUT[4] TMOUT[5] TMOUT[6] TMOUT[7] TMOUT[1]
Timer Clock Source/2
TMOUT[7:0] Interrupt
TMOUT[2]
Timer Clock Source/4
TMOUT[3] TMOUT[4]
Timer Clock Source/8 Timer Clock Source/16
TMOUT[5]
Timer Clock Source/32
TMOUT[6]
Timer Clock Source/64
TMOUT[7]
Timer Clock Source/128
LEDCTL : ADDRESS 12H bit7 bit6 bit5 bit4 bit3 LED1EN LED1 LED0EN LED0 LED1EN: LED1 enable bit 1 = Enabled LED1 control 0 = Disable LED1 control LED1: LED1 output control 1 = Enable LED1 sink output (10mA) 0 = not used LED0EN: LED0 enable bit 1 = Enabled LED0 control 0 = Disable LED0 control
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bit2 GPIO2OEN
bit1 GPIO2
bit0 GPIO2PU
bit7
bit6
bit5
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bit4 LED0: LED0 output control 1 = Enable LED0 sink output (10mA) 0 = not used unimplemented GPIO2OEN: GPIO2 output enable bit 1 = Enabled GPIO2 output 0 = Disable GPIO2 output GPIO2: GPIO2 output H/L GPIO2PU: Internal pull up 10k[ . : ADDRESS 13H bit6 GPIO1OEN bit5 GPIO1 bit4 bit3 bit2 GPIO1PU SPWMO GPIO0OEN bit1 GPIO0 bit0 GPIO0PU
bit3 bit2
bit1 bit0 GPIO
bit7 SPWMEN bit7
bit6
bit5 bit4 bit3 bit2
bit1 bit0
SPMWEN: PWM control 1 = Enabled Software PWM control 0 = Enable Hardware PWM GPIO1OEN: GPIO1 output enable bit 1 = Enabled GPIO1 output 0 = Disable GPIO1 output GPIO1: GPIO1 output H/L GPIO1PU: Internal pull up 10k[ . SPWMO: Software PWM H/L("1" / "0") control bit. GPIO0OEN: GPIO0 output enable bit 1 = Enabled GPIO0 output 0 = Disable GPIO0 output GPIO0: GPIO0 output H/L GPIO0PU: Internal pull up 10k[ .
Not used : ADDRESS 14H Not used : ADDRESS 15H
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11. Instruction Set
The FS3861 instruction set consists of 37 instructions. Each instruction is a 16-bit word with an OPCODE and one or more operands. The detailed descriptions are shown as below.
11.1 Instruction Set Summary
Table11-1: FS3861 Instruction Set
Instruction ADDLW k ADDPCW ADDWF f, d ADDWFC f, d ANDLW k ANDWF f, d BCF f, b BSF f, b BTFSC f, b BTFSS f, b CALL k CLRF f CLRWDT COMF f, d DECF f, d DECFSZ f, d GOTO k HALT INCF f, d INCFSZ f, d IORLW k IORWF f, d MOVFW f MOVLW k MOVWF f NOP RETFIE RETLW k RETURN RLF f, d RRF f, d SLEEP SUBLW k SUBWF f, d SUBWFC f, d XORLW k XORWF f, d Operation [W] [W] + k [PC] [PC] + 1 + [W] [Destination] [f] + [W] [Destination] [f] + [W] + C [W] [W] AND k [Destination] [W] AND [f] [f] 0 [f] 1 Skip if [f] = 0 Skip if [f] = 1 Push PC + 1 and GOTO k [f] 0 Clear watch dog timer [f] NOT([f]) [Destination] [f] -1 [Destination] [f] -1, skip if the result is zero PC k CPU Stop [Destination] [f] +1 [Destination] [f] + 1, skip if the result is zero [W] [W] | k [Destination] [W] | [f] [W] [f] [W] k [f] [W] No operation Pop PC and GIE = 1 RETURN and W = k Pop PC [Destination] [f] [Destination] [f] Stop OSC [W] k - [W] [Destination] [f] - [W] E [Destination] [f] - [W] - C [W] [W] XOR k [Destination] [W] XOR [f] Cycle 1 2 1 1 1 1 1 1 1, 2 1, 2 2 1 1 1 1 1, 2 2 1 1 1, 2 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Flag C, DC, Z None C, DC, Z C, DC, Z Z Z None None None None None Z None Z Z None None None Z None Z Z None None None None None None None C,Z C, Z PD C, DC, Z C, DC, Z C, DC, Z Z Z
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Note: f: memory address (00h ~ 7Fh). W: work register. k: literal field, constant data or label. d: destination select: d=0 store result in W, d=1: store result in memory address f. b: bit select (0~7). [f]: the content of memory address f. PC: program counter. C: Carry flag DC: Digit carry flag Z: Zero flag PD: power down flag TO: watchdog time out flag WDT: watchdog timer counter
11.2 Instruction Description
(By alphabetically)
ADDLW Syntax Operation Flag Affected Description Cycle Example: ADDLW 08h Add Literal to W ADDLW k 0 k FFh [W] [W] + k C, DC, Z The content of Work register add literal "k" in Work register 1 Before instruction: W = 08h After instruction: W = 10h ADDPCW Syntax Operation Flag Affected Description Cycle Example 1: ADDPCW Example 2: ADDPCW Example 3: ADDPCW Add W to PC ADDPCW [PC] [PC] + 1 + [W], [W] < 79h [PC] [PC] + 1 + ([W] - 100h), otherwise None The relative address PC + 1 + W are loaded into PC. 2 Before instruction: W = 7Fh, PC = 0212h After instruction: PC = 0292h Before instruction: W = 80h, PC = 0212h After instruction: PC = 0193h Before instruction: W = FEh, PC = 0212h After instruction: PC = 0211h
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ADDWF Syntax Operation Flag Affected Description Add W to f ADDWF f, d 0 f FFh d [0,1] [Destination] [f] + [W] C, CD, Z Add the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. 1 Before instruction: OPERAND = C2h W = 17h After instruction: OPERAND = C2h W = D9h Before instruction: OPERAND = C2h W = 17h After instruction: OPERAND = D9h W = 17h ADDWFC Syntax Operation Flag Affected Description Add W, f and Carry ADDWFC f, d 0 f FFh d [0,1] [Destination] [f] + [W] + C C, DC, Z Add the content of the W register, [f] and Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. 1 Before instruction: C=1 OPERAND = 02h W = 4Dh After instruction: C=0 OPERAND = 50h W = 4Dh
Cycle Example 1: ADDWF OPERAND, 0
Cycle Example ADDWFC OPERAND,1
Example 2: ADDWF OPERAND, 1
ANDLW Syntax Operation Flag Affected Description
Cycle Example: ANDLW 5Fh
AND literal with W ANDLW k 0 k FFh [W] [W] AND k Z AND the content of the W register with the eight-bit literal "k". The result is stored in the W register. 1 Before instruction: W = A3h After instruction: W = 03h
ANDWF Syntax Operation Flag Affected Description
Cycle Example 1: ANDWF OPERAND,0 Example 2: ANDWF OPERAND,1
AND W and f ANDWF f, d 0 f FFh d [0,1] [Destination] [W] AND [f] Z AND the content of the W register with [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f. 1 Before instruction: W = 0Fh, OPERAND = 88h After instruction: W = 08h, OPERAND = 88h Before instruction: W = 0Fh, OPERAND = 88h After instruction: W = 88h, OPERAND = 08h
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BCF Syntax Operation Flag Affected Description Cycle Example: BCF FLAG, 2 Bit Clear f BCF f, b 0 f FFh 0b7 [f] 0 None Bit b in [f] is reset to 0. 1 Before instruction: FLAG = 8Dh After instruction: FLAG = 89h BSF Syntax Operation Flag Affected Description Cycle Example: BSF FLAG, 2 Bit Set f BSF f, b 0 f FFh 0b7 [f] 1 None Bit b in [f] is set to 1. 1 Before instruction: FLAG = 89h After instruction: FLAG = 8Dh
BTFSC Syntax Operation Flag Affected Description
Cycle Example: Node BTFSC FLAG, 2 OP1 : OP2 :
Bit Test skip if Clear BTFSC f, b 0 f FFh 0b7 Skip if [f] = 0 None If bit 'b' in [f] is 0, the next fetched instruction is discarded and a NOP is executed instead of making it a two-cycle instruction. 1, 2 Before instruction: PC = address (Node) After instruction: If FLAG<2> = 0 PC = address(OP2) If FLAG<2> = 1 PC = address(OP1)
BTFSS Syntax Operation Flag Affected Description
Cycle Example: Node BTFSS FLAG, 2 OP1 : OP2 :
Bit Test skip if Set BTFSS f, b 0 f FFh 0b7 Skip if [f] = 1 None If bit 'b' in [f] is 1, the next fetched instruction is discarded and a NOP is executed instead of making it a two-cycle instruction. 1, 2 Before instruction: PC = address (Node) After instruction: If FLAG<2> = 0 PC = address(OP1) If FLAG<2> = 1 PC = address(OP2)
CALL Syntax Operation Flag Affected Description
Cycle
Subroutine CALL CALL k 0 k 1FFFh Push Stack [Top Stack] PC + 1 PC k None Subroutine Call. First, return address PC + 1 is pushed onto the stack. The immediate address is loaded into PC. 2
CLRF Syntax Operation Flag Affected Description Cycle Example: CLRF WORK
Clear f CLRF f 0 f 255 [f] 0 None Reset the content of memory address f 1 Before instruction: WORK = 5Ah After instruction: WORK = 00h
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CLRWDT Syntax Operation Flag Affected Description Cycle Example: CLRWDT Clear watch dog timer CLRWDT Watch dog timer counter will be reset None CLRWDT instruction will reset watch dog timer counter. 1 After instruction: WDT = 0 TO = 1 PD = 1 COMF Syntax Operation Flag Affected Description Complement f COMF f, d 0 f 255 d [0,1] [f] NOT([f]) Z [f] is complemented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f] 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = DCh, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = DCh
Cycle Example 1: COMF OPERAND,0 Example 2: COMF OPERAND,1
DECF Syntax Operation Flag Affected Description
Cycle Example 1: DECF OPERAND,0 Example 2: DECF OPERAND,1
Decrement f DECF f, d 0 f 255 d [0,1] [Destination] [f] -1 Z [f] is decremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 22h, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 22h
DECFSZ Syntax
Decrement f, skip if zero DECFSZ f, d 0 f FFh d [0,1] Operation [Destination] [f] -1, skip if the result is zero Flag Affected None Description [f] is decremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. If the result is 0, then the next fetched instruction is discarded and a NOP is executed instead of making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node DECFSZ FLAG, 1 PC = address (Node) OP1 : After instruction: OP2 : [FLAG] = [FLAG] - 1 If [FLAG] = 0 PC = address(OP1) If [FLAG] 0 PC = address(OP2)
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GOTO Syntax Operation Flag Affected Description Cycle Unconditional Branch GOTO k 0 k 1FFFh PC k None The immediate address is loaded into PC. 2 HALT Syntax Operation Flag Affected Description Stop CPU Core Clock HALT CPU Stop None CPU clock is stopped. Oscillator is running. CPU can be waked up by internal and external interrupt sources. 1
Cycle
INCF Syntax Operation Flag Affected Description
Cycle Example 1: INCF OPERAND,0 Example 2: INCF OPERAND,1
Increment f INCF f, d 0 f FFh d [0,1] [Destination] [f] +1 Z [f] is incremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 24h, OPERAND = 23h Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 24h
INCFSZ Syntax
Increment f, skip if zero INCFSZ f, d 0 f FFh d [0,1] Operation [Destination] [f] + 1, skip if the result is zero Flag Affected None Description [f] is incremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. If the result is 0, then the next fetched instruction is discarded and a NOP is executed instead of making it a two-cycle instruction. Cycle 1, 2 Example: Before instruction: Node INCFSZ FLAG, 1 PC = address (Node) OP1 : After instruction: OP2 : [FLAG] = [FLAG] + 1 If [FLAG] = 0 PC = address(OP2) If [FLAG] 0 PC = address(OP1)
IORLW Syntax Operation Flag Affected Description
Cycle Example: IORLW
85H
Inclusive OR literal with W IORLW k 0 k FFh [W] [W] | k Z Inclusive OR the content of the W register and the eight-bit literal "k". The result is stored in the W register. 1 Before instruction: W = 69h After instruction: W = EDh
IORWF Syntax Operation Flag Affected Description
Cycle Example: IORWF OPERAND,1
Inclusive OR W with f IORWF f, d 0 f FFh d [0,1] [Destination] [W] | [f] Z Inclusive OR the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = ABh
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MOVFW Syntax Operation Flag Affected Description Cycle Example: MOVFW Move f to W MOVFW f 0 f FFh [W] [f] None Move data from [f] to the W register. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 23h, OPERAND = 23h MOVLW Syntax Operation Flag Affected Description Cycle Example: MOVLW Move literal to W MOVLW k 0 k FFh [W] k None Move the eight-bit literal "k" to the content of the W register. 1 Before instruction: W = 88h After instruction: W = 23h
OPERAND
23H
MOVWF Syntax Operation Flag Affected Description Cycle Example: MOVWF
OPERAND
Move W to f MOVWF f 0 f FFh [f] [W] None Move data from the W register to [f]. 1 Before instruction: W = 88h, OPERAND = 23h After instruction: W = 88h, OPERAND = 88h
NOP Syntax Operation Flag Affected Description Cycle
No Operation NOP No Operation None No operation. NOP is used for one instruction cycle delay. 1
RETFIE Syntax Operation Flag Affected Description
Cycle
Return from Interrupt RETFIE [Top Stack] => PC Pop Stack 1 => GIE None The program counter is loaded from the top stack, then pop stack. Setting the GIE bit enables interrupts. 2
RETLW Syntax Operation Flag Affected Description
Return and move literal to W RETLW k 0 k FFh [W] k [Top Stack] => PC Pop Stack None Move the eight-bit literal "k" to the content of the W register. The program counter is loaded from the top stack, then pop stack.
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Return Syntax Operation Flag Affected Description Cycle Return from Subroutine RETURN [Top Stack] => PC Pop Stack None The program counter is loaded from the top stack, then pop stack. 2 RLF Syntax Operation Rotate left [f] through Carry RLF f, d 0 f FFh d [0,1] [Destination] [f] [Destination<0>] C C [f<7>] C, Z [f] is rotated one bit to the left through the Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: C=0 W = 88h, OPERAND = E6h After instruction: C=1 W = 88h, OPERAND = CCh
Flag Affected Description
Cycle Example: RLF OPERAND, 1
RRF Syntax Operation
Flag Affected Description
Rotate right [f] through Carry RRF f, d 0 f FFh d [0,1] [Destination] [f] [Destination<7>] C C [f<7>] C [f] is rotated one bit to the right through the Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. 1 Before instruction: C=0 OPERAND = 95h After instruction: C=1 W = 4Ah, OPERAND = 95h
SLEEP Syntax Operation Flag Affected Description Cycle
Oscillator stop SLEEP CPU oscillator is stopped PD CPU oscillator is stopped. CPU can be waked up by external interrupt sources. 1
Cycle Example: RRF OPERAND, 0
Please make sure that all interrupt flags are cleared before running SLEEP; "NOP" command must follow HALT and SLEEP commands.
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SUBLW Syntax Operation Flag Affected Description Subtract W from literal SUBLW k 0 k FFh [W] k - [W] C, DC, Z Subtract the content of the W register from the eight-bit literal "k". The result is stored in the W register. 1 Before instruction: W = 01h After instruction: W = 01h C=1 Z=0 Before instruction: W = 02h After instruction: W = 00h C=1 Z=1 Before instruction: W = 03h After instruction: W = FFh C=0 Z=0 SUBWF Syntax Operation Flag Affected Description Subtract W from f SUBWF f, d 0 f FFh d [0,1] [Destination] [f] - [W] C, DC, Z Subtract the content of the W register from [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f], 1 Before instruction: OPERAND = 33h, W = 01h After instruction: OPERAND = 32h C=1 Z=0 Before instruction: OPERAND = 01h, W = 01h After instruction: OPERAND = 00h C=1 Z=1 Before instruction: OPERAND = 04h, W = 05h After instruction: OPERAND = FFh C=0 Z=0
Cycle Example 1: SUBLW 02H
Cycle Example 1: SUBWF OPERAND, 1
Example 2: SUBLW 02H
Example 2: SUBWF OPERAND, 1
Example 3: SUBLW 02H
Example 3: SUBWF OPERAND, 1
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SUBWFC Syntax Subtract W and Carry from f SUBWFC f, d 0 f FFh d [0,1] E Operation [Destination] [f] - [W] -C Flag Affected C, DC, Z Description Subtract the content of the W register from [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. Cycle 1 Example 1: Before instruction: SUBWFC OPERAND, 1 OPERAND = 33h, W = 01h C=1 After instruction: OPERAND = 32h, C = 1, Z = 0 Example 2: Before instruction: SUBWFC OPERAND, 1 OPERAND = 02h, W = 01h C=0 After instruction: OPERAND = 00h, C = 1, Z = 1 Example 3: Before instruction: SUBWFC OPERAND, 1 OPERAND = 04h, W = 05h C=0 After instruction: OPERAND = FEh, C = 0, Z = 0 XORWF Syntax Exclusive OR W and f XORWF f, d 0 f FFh d [0,1] Operation [Destination] [W] XOR [f] Flag Affected Z Description Exclusive OR the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f]. Cycle 1 Example: Before instruction: XORWF OPERAND, 1 OPERAND = 5Fh, W = ACh After instruction: OPERAND = F3h
XORLW Syntax Operation Flag Affected Description
Cycle Example: XORLW
5Fh
Exclusive OR literal with W XORLW k 0 k FFh [W] [W] XOR k Z Exclusive OR the content of the W register and the eight-bit literal "k". The result is stored in the W register. 1 Before instruction: W = ACh After instruction: W = F3h
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12. Package Information
12.1 Package Outline & Dimensions
SYMBOL A A1 A2 b c e D E E1 L h L1 ZD R1 R 1 2 JEDEC
DIMENSION IN MM MIN 1.35 0.10 0.20 0.18 0.635 BASIC 4.80 5.79 3.81 0.41 0.25 0.254 BASIC 0.229 REF 0.20 0.20 0 0 5 10 8 8 15 0.33 4.90 5.99 3.91 0.635 5.00 6.20 3.99 1.27 0.50 NOM 1.63 0.15 MAX 1.75 0.25 1.50 0.30 0.25
DIMENSION IN INCH MIN 0.053 0.004 0.008 0.007 0.025 BASIC 0.189 0.228 0.150 0.016 0.010 0.010 BASIC 0.009 REF 0.008 0.008 0 0 5 10 8 8 15 0.013 0.193 0.236 0.154 0.025 0.197 0.244 0.157 0.050 0.020 NOM 0.064 0.006 MAX 0.069 0.010 0.059 0.012 0.010
MO-137(AB)
Notes: Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not exceed 0.06 inch per side. Fortune Semiconductor Corp.
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